Venkata Rajasekhara Reddy Gosula

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Manage a 10 person ASIC team located partly in Carlsbad, and partly in Kuala Lumpur, Malaysia in the design of the digital logic for a variety of wireless ASICs, such as Wireless Keyboard and Mouse, Electronic Shelf Labeling and Wireless OFDM Audio Speakers. Improved ASIC design process, methodology and tools usage in the areas of verification, regressions, scripting, code linting, code coverage, testbench creation, design rule adherence, SystemVerilog, Assertions and DFT. Setup an effective method for communication between engineers in Malaysia and US to work on common projects, including but not limited to CVS, status reports, biweekly conference calls, project conference calls, skype usage, travel to Malaysia to train engineers and goal setting/reviews.

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Designed and Verified 1 million gate PHY receiver section of a 5 million gate SOC. Implemented MoCA OFDM PHY receiver, including AGC, Preamble detection, FFT integration, Time Tracking, Frequency Tracking, Correlators, and Channel estimation. Bit matched Verilog with C system simulation, supported lab FGPA emulation, and supported synthesis of circuits up to 100MHz. ASIC sampleable after first tapeout. Designed and integrated memory controller for SDRAM, Flash and SRAM.

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Led team in design environment setup and implementation of Wireless LAN ASICs. Responsible for digital section of mixed signal Bluetooth Radio chip. Implemented Demodulator, Correlator and Time Tracking Circuits. Delivered GDS II of digital section to the analog group responsible for the tapeout. Led team that implemented the 802.11a OFDM PHY. Implemented RF Interface, MAC Interface, Transmit Chain and FFT. Coordinated integration of AGC, Viterbi, and Receive chain into the PHY. Worked closely with system group to define requirements, measure performance and verify correctness of Verilog implementation. Used Verilog-XL, Synopsys and Avanti.

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Director, ASIC Design - Formatter Group - July 1996 to January 2000 Managed a team of up to 10 ASIC design engineers and mathematicians in the design of an evolving 250K gate design common to AT, SCSI and Fiberchannel Disk Drive Controllers with transfer rates up to 1Gbit/sec. Supported Controller ASIC design, test, fabrication, and applications for most Seagate Drives. Maintained detailed knowledge of design, and provided technical support and direction. Recruited and built a cohesive team. Defined future requirements together with all internal Drive groups. Senior Staff (ASIC) Design Engineer - August 1992 to July 1996 Designed Disc Drive controller ASIC's; Redesigned Clock and DRAM controllers. Verified gate-level simulation and generated test vectors. Led effort to transition department from schematics to VHDL. Designed and synthesized Reed Solomon Error Correction circuit using VHDL. Synthesized entire ASIC with multiple clock domains and asynchronous interfaces. Taught Unix class to 20 engineers.

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Designed and verified simulation accelerator ASICs. Worked on designing both, a gate level simulation accelerator(XP) and a VHDL hardware accelerator(ViP). Defined requirements, designed architecture; wrote, debugged, documented, and synthesized VHDL code. Verified gate-level simulation and generated test vectors. Wrote diagnostic and run-time software.