Héctor Pettenghi Roldán

Pós-doutorado

Formação complementar

Idiomas

Áreas de atuação

Organização de eventos

Participação em eventos

Participação em bancas

Orientou

Produções bibliográficas

• SOUSA, LEONEL AUGUSTO ; PALUDO, ROGERIO ; MARTINS, PAULO ; PETTENGHI, HECTOR . Towards the Integration of Reverse Converters into the RNS Channels. IEEE TRANSACTIONS ON COMPUTERS , v. 1, p. 1-1, 2019.

• PETTENGHI, HECTOR ; PALUDO, ROGERIO ; MATOS, ROBERTO ; LYAKHOV, PAVEL A. . Efficient RNS Reverse Converters for Moduli Sets with Dynamic Ranges Up to $$(10n+1)$$(10n+1)-bit. CIRCUITS SYSTEMS AND SIGNAL PROCESSING , v. 37, p. 5178-5196, 2018.

• PETTENGHI, HECTOR ; CHAVES, RICARDO ; MATOS, ROBERTO DE ; SOUSA, LEONEL . Method for designing two levels RNS reverse converters for large dynamic ranges. Integration (Amsterdam. Print) , v. 55, p. 22-29, 2016.

• PETTENGHI, H. ; PRATAS, F. ; SOUSA, L. . Method for Designing Efficient Mixed Radix Multipliers. Circuits, Systems, and Signal Processing , v. 1, p. 1, 2014.

• PETTENGHI, HECTOR ; SOUSA, LEONEL . Method to Design General RNS Reverse Converters for Extended Moduli Sets. IEEE Transactions on Circuits and Systems II: Express Briefs , v. 60, p. 877-881, 2013.

• PETTENGHI, HECTOR ; CHAVES, RICARDO ; SOUSA, LEONEL . RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to $(8n+1)$ -bit. IEEE Transactions on Circuits and Systems. I, Regular Papers (Online) , v. 60, p. 1487-1500, 2013.

• PETTENGHI, HECTOR ; JAYASINGHE, DARSHANA ; AMBROSE, JUDE ANGELO ; SOUSA, LEONEL . Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks. IET Circuits, Devices & Systems (Print) , v. 7, p. 283-293, 2013.

• PETTENGHI, HECTOR ; COTOFANA, SORIN ; SOUSA, LEONEL . EFFICIENT METHOD FOR DESIGNING MODULO {2 k} MULTIPLIERS. Journal of Circuits, Systems, and Computers , v. 23, p. 1450001, 2013.

• PETTENGHI, HÉCTOR ; AVEDILLO, MARÍA J. ; QUINTANA, JOSÉ M. . Improved Nanopipelined RTD Adder Using Generalized Threshold Gates. IEEE Transactions on Nanotechnology , v. 10, p. 155-162, 2011.

• QUINTANA, J.M. ; AVEDILLO, M.J. ; NUNEZ, J. ; ROLDAN, H.P. . Operation Limits for RTD-Based MOBILE Circuits. IEEE Transactions on Circuits and Systems. I, Regular Papers (Print) , v. 56, p. 350-363, 2009.

• PETTENGHI, HECTOR ; AVEDILLO, MARÍA J. ; QUINTANA, JOSÉ M. . Using multi-threshold threshold gates in RTD-based logic design: A case study. Microelectronics (Luton) (Cessou em 1978. Cont. ISSN 0959-8324 Microelectronics Journal) , v. 39, p. 241-247, 2008.

• AVEDILLO, M.J. ; QUINTANA, J.M. ; ROLDAN, H.P. . Increased Logic Functionality of Clocked Series-Connected RTDS. IEEE Transactions on Nanotechnology , v. 5, p. 606-611, 2006.

• AVEDILLO, M.J. ; QUINTANA, J.M. ; PETTENGHI, H. . Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors. IEEE Transactions on Circuits and Systems. II, Analog and Digital Signal Processing (Cessou em 2002. Funfiu-se com ISSN 1057-7122 e 1549-8328) , v. 53, p. 334-338, 2006.

• PETTENGHI, H. ; AVEDILLO, M.J. ; QUINTANA, J.M. . Single phase clock scheme for mobile logic gates. Electronics Letters , v. 42, p. 1382, 2006.

• AVEDILLO, M.J. ; QUINTANA, J.M. ; PETTENGHI, H. ; KELLY, P.M. ; THOMPSON, C.J. . Multi-threshold threshold logic circuit design using resonant tunnelling devices. Electronics Letters , v. 39, p. 1502, 2003.

• F. Cabrera ; F. Rangel ; PETTENGHI, H. . Introducing Asymmetry in a CMOS Latch to Obtain Inherent Power-On-Reset Behaviour. In: LASCAS, 2018, Armenia. 10th IEEE Latin American Symposium on Circuits and Systems (LASCAS), 2019.

• PETTENGHI, H. ; R. De Matos ; PALUDO, R. ; P. Lyakhov . Efficient Implementation of Modular Multiplication by Constants Applied to RNS Reverse Converters. In: 2017 IEEE International Symposium on Circuits & Systems, 2017, Baltimore. Efficient Implementation of Modular Multiplication by Constants Applied to RNS Reverse Converters, 2017.

• PETTENGHI, HECTOR ; DE MATOS, ROBERTO ; MOLAHOSSEINI, AMIR . RNS reverse converters for moduli sets with dynamic ranges of 9n-bit. In: 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), 2016, Florianopolis. 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), 2016. p. 143.

• PETTENGHI, H. ; SOUSA, LEONEL . RNS Reverse Converters based on the New Chinese Remainder Theorem I. In: International Symposium on Circuits and Systems (ISCAS15), 2015, Lisboa, Portugal. Proceedings of Int. Symp. on Circuits and Syst. (ISCAS15), 2015.

• PETTENGHI, H. ; SOUSA, LEONEL ; AMBROSE, JUDE ANGELO . Novel methodology to improve Multi-moduli architectures for Binary-to-RNS conversion. In: XXX Conference on Design of Circuits and Integrated Systems, 2015, Estoril. Conference on Design of Circuits and Integrated Systems, 2015.

• PETTENGHI, H. ; CHAVES, RICARDO ; SOUSA, LEONEL . Method for designing Multi-Channel RNS Architectures to prevent Power Analysis SCA. In: Int. Symp. on Circuits and Syst. (ISCAS14), 2014, Melbourne. Proceedings of Int. Symp. on Circuits and Syst. (ISCAS14), 2014.

• AMBROSE, JUDE ANGELO ; PETTENGHI, HECTOR ; SOUSA, LEONEL . DARNS:A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks. In: 2013 18th Asia and South Pacific Design Automation Conference (ASPDAC), 2013, Yokohama. 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013. p. 620.

• PETTENGHI, H. ; CHAVES, RICARDO ; SOUSA, LEONEL . Method for designing modulo {2^nk} Binary-to-RNS converters. In: Conference on Design of Circuits and Integrated Systems (2013), 2013, San Sebastian (Spain). Proceedings of Conference on Design of Circuits and Integrated Systems, 2013.

• MATUTINO, PEDRO MIGUENS ; PETTENGHI, HECTOR ; CHAVES, RICARDO ; SOUSA, LEONEL . RNS Arithmetic Units for Modulo {2^n+-k}. In: 2012 15th Euromicro Conference on Digital System Design (DSD), 2012, Cesme. 2012 15th Euromicro Conference on Digital System Design, 2012. p. 795.

• PETTENGHI, HECTOR ; SOUSA, LEONEL ; AMBROSE, JUDE ANGELO . Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion. In: 2012 17th Asia and South Pacific Design Automation Conference (ASPDAC), 2012, Sydney. 17th Asia and South Pacific Design Automation Conference, 2012. p. 819.

• MATUTINO, P. M. ; PETTENGHI, HECTOR ; CHAVES, RICARDO ; SOUSA, LEONEL . Multiplier-based binary-to-RNS converter modulo {2nk}. In: Conference on Design of Circuits and Integrated Systems (DCIS), 2011, Albufeira (Portugal). Multiplier-based binary-to-RNS converter modulo {2nk}, 2011.

• PETTENGHI, HECTOR ; CHAVES, RICARDO ; SOUSA, LEONEL ; AVEDILLO, MARIA J. . An improved RNS generator 2n k based on threshold logic. In: 2010 18th IEEE/IFIP International Conference on VLSI and SystemonChip (VLSISoC), 2010, Madrid. 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2010. p. 119.

• PETTENGHI, HECTOR ; AVEDILLO, MARIA J. ; QUINTANA, JOSE M. . A novel contribution to the RTD-based threshold logic family. In: 2008 IEEE International Symposium on Circuits and Systems ISCAS 2008, 2008, Seattle. 2008 IEEE International Symposium on Circuits and Systems, 2008. p. 2350.

• PETTENGHI, HÉCTOR ; AVEDILLO, MARIA J. ; QUINTANA, J.M. . RTD based Logic Circuits Using Generalized Threshold Gates. In: Conference on Design of Circuits and Integrated Systems (2008), 2008, Grenoble (France). Proceedings of Conference on Design of Circuits and Integrated Systems, 2008.

• PETTENGHI, HECTOR ; AVEDILLO, MARIA J. ; QUINTANA, JOSE M. . Non Return Mobile Logic Family. In: 2007 IEEE International Symposium on Circuits and Systems, 2007, New Orleans. 2007 IEEE International Symposium on Circuits and Systems, 2007. p. 125.

• ROLDAN, H.P. ; AVEDILLO, MARIA J. ; QUINTANA, J.M. . Single Phase Clock Scheme for Mobile Based Circuits. In: Conference on Design of Circuits and Integrated Systems (2006), 2006, Barcelona (Spain). Conference on Design of Circuits and Integrated Systems, 2006.

• QUINTANA, J.M. ; AVEDILLO, MARIA J. ; PETTENGHI, H. . Implementación de lógica umbral y multiumbral con RTDs. In: IBERCHIP, 2006, San José. IBERCHIP, 2006.

• QUINTANA, J.M. ; AVEDILLO, M.J. ; PETTENGHI, H. . Self-latching operation limits for MOBILE circuits. In: 2006 IEEE International Symposium on Circuits and Systems, 2006, Island of Kos. 2006 IEEE International Symposium on Circuits and Systems. p. 4.

• PETTENGHI, H. ; AVEDILLO, MARÍA J. ; QUINTANA, J.M. . Using Multi-Threshold Threshold Gates in RTDbased Logic Design. A Case Study. In: European Nano Systems 2005 (ENS), 2005, Paris. Proceedings of the European Nano Systems 2005 (ENS), 2005.

• ROLDAN, H.P. ; AVEDILLO, MARIA J. ; QUINTANA, J.M. . Nanopipelined RTD adders using Multi-Threshold Threshold Gates. In: Conference on Design of Circuits and Integrated Systems (2005), 2005, Lisbon (Portugal). Proceedings of Conference on Design of Circuits and Integrated Systems, 2005.

• QUINTANA, J.M. ; AVEDILLO, MARÍA J. ; PETTENGHI, HECTOR . Design of Residue Generators using Threshold Logic. In: International Symposium on Micro-NanoMechatronics and Human Science, 2005, Nagoya. International Symposium on Micro-NanoMechatronics and Human Science, 2005. v. 3.

• AVEDILLO, M.J. ; QUINTANA, J.M. ; PETTENGHI, H. . Logic Models Supporting the Design of MOBILE-based RTD Circuits. In: 2005 IEEE International Conference on ApplicationSpecific Systems, Architecture Processors (ASAP'05), 2005, Samos. 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05). p. 254.

• QUINTANA, J.M. ; AVEDILLO, M.J. ; PETTENGHI, H. . Programmable logic gate based on resonant tunnelling devices. In: 2004 IEEE International Symposium on Circuits and Systems, 2004, Vancouver. 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512). p. III.

• QUINTANA, J.M. ; AVEDILLO, M.J. ; PETTENGHI, H. . RTD-based compact programmable gates. In: 2004 IEEE International Joint Conference on Neural Networks, 2004, Budapest. 2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No.04CH37541). p. 2637.

• PETTENGHI, H. ; AVEDILLO, M.J. ; QUINTANA, J.M. . Useful logic blocks based on clocked series-connected RTDs. In: 4th IEEE Conference on Nanotechnology, 2004., 2004, Munich. 4th IEEE Conference on Nanotechnology, 2004.. p. 593.

• PETTENGHI, H. ; AVEDILLO, MARIA J. ; QUINTANA, J.M. . A CAD tool for the design of RTD programmable gates based on MOBILE. In: Conference on Design of Circuits and Integrated Systems (2004), 2004, Burdeos. Proceedings of Conference on Design of Circuits and Integrated Systems, 2004.

• QUINTANA, J.M. ; AVEDILLO, MARIA J. ; PETTENGHI, H. . Design of Residue Generators Modulo-3 by using Threshold Logic. In: Conference on Design of Circuits and Integrated Systems, 2003, Ciudad Real (Spain). Proceedings of Conference on Design of Circuits and Integrated Systems, 2003.

• PETTENGHI, H. ; CHAVES, RICARDO ; SOUSA, LEONEL . Multiplicative Inverses Validations for Moduli Sets with Dynamic Ranges of (5n + )-bit 2012 (Relatório Ténico).

Projetos de pesquisa

• 2020 - Atual

  Pesquisa e desenvolvimento de satélites universitários de pequeno porte, Situação: Em andamento; Natureza: Pesquisa. , Integrantes: Héctor Pettenghi Roldán - Coordenador / Eduardo Bezerra - Integrante / Anderson Wedderhoff Spengler - Integrante.

• 2014 - 2018

  Embedded Multi-Core Systems for Mixed Criticality Applications in Dynamic and Changeable Real-Time Environments (EMC2), Ref: 621429 FP7-JTI, Descrição: The EMC2 project focuses on the industrialization of European research outcomes and builds on the results of previous ARTEMIS, European and National projects. It provides the paradigm shift to a new and sustainable system architecture which is suitable to handle open dynamic systems.. , Situação: Concluído; Natureza: Pesquisa. , Integrantes: Héctor Pettenghi Roldán - Integrante / CHAVES, RICARDO - Coordenador.

• 2014 - 2015

  Infraestrutura automática para computação baseada em RNS, Ref: EXPL/EEI-ELC/1572/2013., Descrição: This exploratory work herein proposed will allow this research team to further explore the development of a RNS framework capable of automatically deriving efficient Residual Number Systems improving the computation of arithmetic, signal processing and cryptographic algorithms. More significantly, with this framework we hope to further motivate the use of RNS by having a mechanism that eliminates the complexity of developing computational architectures that explore this numbering system arithmetic. This will also motivate the research community working on RNS to further improve the RNS state of the art.. , Situação: Concluído; Natureza: Pesquisa. , Alunos envolvidos: Graduação: (1) / Doutorado: (1) . , Integrantes: Héctor Pettenghi Roldán - Integrante / CHAVES, RICARDO - Coordenador., Financiador(es): Fundação de Ciência e Tecnologia - Auxílio financeiro.

• 2011 - 2013

  "The power of the short Tools and Algorithms for next Generation Sequencing applications" (TAGS), Ref: PTDC/EIAEIA/ 112283/2009, Descrição: TAGS project aims at developing new algorithms an tools for next generation DNA sequencing applications. Such challenges will be addressed by developing accurate error models, approximate indexing methods, distributed data structures and exploiting multi-core system architectures.. , Situação: Concluído; Natureza: Pesquisa. , Integrantes: Héctor Pettenghi Roldán - Integrante / Nuno Roma - Coordenador.

• 2008 - 2012

  "Design and implementation of multivalued circuits using devices with NDR characteristics" (MV-NDR), Ref: P07-TIC02961., Descrição: Extensão do projecto QUDOS para a pesquisa de sistemas multi-nivel usando RTDs.. , Situação: Concluído; Natureza: Pesquisa. , Integrantes: Héctor Pettenghi Roldán - Integrante / QUINTANA, J.M. - Coordenador / AVEDILLO, M.J. - Integrante / Maria Angeles Jalon Victori - Integrante / Jose Alberto Villegas Calvo - Integrante.

• 2008 - 2010

  "Short Range Radio" (SR2), Ref: PSI-020400- 2008-71, Descrição: Projecto para o desenvolvimento em tecnologías nano-métricas CMOS de bloques analógicos para aplicações de RF.. , Situação: Concluído; Natureza: Pesquisa. , Integrantes: Héctor Pettenghi Roldán - Integrante / Adoración Rueda - Coordenador.

• 2007 - 2009

  "Circuit Design and Implementation of Nanomicro-Devices using devices with NDR characteristics" (NDR). Ref: TEC2007-67245/MIC., Descrição: Extension of the QUDOS project.. , Situação: Concluído; Natureza: Pesquisa. , Integrantes: Héctor Pettenghi Roldán - Integrante / QUINTANA, J.M. - Integrante / AVEDILLO, M.J. - Coordenador.

• 2006 - 2009

  "Technical design and test of integrated mixed circuits in emerging technologies", Ref: EXC/2005/TIC-927, Descrição: This project is focused on the fabrication process of the first RTDs, starting from the layout and finishing with circuit test using a proves station.. , Situação: Concluído; Natureza: Pesquisa. , Integrantes: Héctor Pettenghi Roldán - Integrante / QUINTANA, J.M. - Integrante / AVEDILLO, M.J. - Integrante / Adoración Rueda - Coordenador.

• 2005 - 2007

  "Wireless Technologies for small area Networks with Embedded Security & Safety" (WITNESS), Ref: FIT-330100-2006-43., Descrição: Desenvolvimiento de componentes de uma plataforma aberta para o projecto de redes sem fios de baixo custo e baixo consumo com prestações de segurança embebidas.. , Situação: Concluído; Natureza: Pesquisa. , Integrantes: Héctor Pettenghi Roldán - Integrante / Adoración Rueda - Coordenador.

• 2004 - 2006

  "Design and implementation of monolithic nano-microelectronic circuits based on resonant tunnel effect" (Ref: TEC2004-02948/MIC), Descrição: The extension of the QDOS project in order to explore the limits of the RTDs. , Situação: Concluído; Natureza: Pesquisa. , Integrantes: Héctor Pettenghi Roldán - Integrante / QUINTANA, J.M. - Coordenador / AVEDILLO, M.J. - Integrante.

• 2002 - 2005

  "Poly-SiGe for CMOS Backend Integration of MEM" (SiGEM), Ref: IST-2001-37681-SIGEM, Descrição: In the SiGeM project several low-temperature deposition methods (CVD, PECVD, LPCVD) were developed, and were evaluated with respect to growth rate and material quality. The interconnection technology to the underlying CMOS circuitry was also developed. The capabilities of this new integration technology will be demonstrated in a monolithic high-performance rate-of-turn sensor, currently considered the most demanding MEMs application in terms of material properties of the structural layer (thickness > 10mm, stress gradient < 0.3MPa/mm) and signal processing circuitry (capacitance resolution in the aF range, SNR > 110 dB). System partitioning will combine analog and DSP circuit techniques to maximize resolution and stability. Parasitic electrical coupling within different parts of the system has been analyzed, and countermeasures to reduce it have been incorporated in the design. , Situação: Concluído; Natureza: Pesquisa. , Integrantes: Héctor Pettenghi Roldán - Integrante / José Luis Huertas - Coordenador / Juan Ramos Martos - Integrante / Joaquin Ceballos - Integrante / Antonio Ragel - Integrante / Jose Miguel Mora - Integrante / Alberto Arias - Integrante / Miguel Angel Lagos - Integrante.

• 2002 - 2004

  "Quantum Tunneling Device Technology on Silicon" (QUDOS), Ref: IST-2001-32358., Descrição: The subject of this proposal is the design and fabrication of negative-differential resistance (NDR) devices on silicon substrate. The objective is a theoretical and experimental assessment of emerging NDR technologies providing a robust and manufacturability device operation on the nano-scale.. , Situação: Concluído; Natureza: Pesquisa. , Integrantes: Héctor Pettenghi Roldán - Integrante / QUINTANA, J.M. - Coordenador / AVEDILLO, M.J. - Integrante.

• 2001 - 2005

  "Integrated Opto-Nanomechanical Biosensor for functional Genomic Analysis" (OPTONANOGEN) Ref: IST-2001-37239., Descrição: Development of a portable multibíosensor microsystem (OPTONANOGEN) able to detect hybridization of nucleíc acids partly complementary to human genes with femtomolar sensitivity and ability for discerning single base variations.. , Situação: Concluído; Natureza: Pesquisa. , Integrantes: Héctor Pettenghi Roldán - Integrante / Adoración Rueda - Coordenador.

• 2001 - 2003

  Tools and Methods for IP, Ref: A511, Descrição: Contribution to the next generation of IP reuse for SoC design.. , Situação: Concluído; Natureza: Pesquisa. , Integrantes: Héctor Pettenghi Roldán - Integrante / Adoración Rueda - Coordenador.

Projetos de desenvolvimento

• 2013 - Atual

  Trustworthy Manufacturing and Utilization of Secure Devices, Descrição: This COST action aims at creating a European network of competence and experts on all aspects of hardware security including design, manufacturing, testing, reliability, validation and utilization. The network will play a key role in developing solutions responding to the hardware security challenges, hence strengthening the position of Europe in the field.". , Situação: Em andamento; Natureza: Desenvolvimento. , Integrantes: Héctor Pettenghi Roldán - Coordenador / CHAVES, RICARDO - Coordenador.

• 2013 - Atual

  Trustworthy Manufacturing and Utilization of Secure Devices, Descrição: This COST action aims at creating a European network of competence and experts on all aspects of hardware security including design, manufacturing, testing, reliability, validation and utilization. The network will play a key role in developing solutions responding to the hardware security challenges, hence strengthening the position of Europe in the field.". , Situação: Em andamento; Natureza: Desenvolvimento. , Integrantes: Héctor Pettenghi Roldán - Coordenador / CHAVES, RICARDO - Coordenador.

• 2013 - Atual

  Trustworthy Manufacturing and Utilization of Secure Devices, Descrição: This COST action aims at creating a European network of competence and experts on all aspects of hardware security including design, manufacturing, testing, reliability, validation and utilization. The network will play a key role in developing solutions responding to the hardware security challenges, hence strengthening the position of Europe in the field.". , Situação: Em andamento; Natureza: Desenvolvimento. , Integrantes: Héctor Pettenghi Roldán - Integrante / CHAVES, RICARDO - Coordenador.

• 2013 - 2016

  Trustworthy Manufacturing and Utilization of Secure Devices, Descrição: This COST action aims at creating a European network of competence and experts on all aspects of hardware security including design, manufacturing, testing, reliability, validation and utilization. The network will play a key role in developing solutions responding to the hardware security challenges, hence strengthening the position of Europe in the field.". , Situação: Concluído; Natureza: Desenvolvimento. , Integrantes: Héctor Pettenghi Roldán - Integrante / CHAVES, RICARDO - Coordenador.

• 2013 - 2016

  Trustworthy Manufacturing and Utilization of Secure Devices, Descrição: This COST action aims at creating a European network of competence and experts on all aspects of hardware security including design, manufacturing, testing, reliability, validation and utilization. The network will play a key role in developing solutions responding to the hardware security challenges, hence strengthening the position of Europe in the field.". , Situação: Concluído; Natureza: Desenvolvimento. , Integrantes: Héctor Pettenghi Roldán - Integrante / CHAVES, RICARDO - Coordenador.

• 2013 - 2016

  Trustworthy Manufacturing and Utilization of Secure Devices, Descrição: This COST action aims at creating a European network of competence and experts on all aspects of hardware security including design, manufacturing, testing, reliability, validation and utilization. The network will play a key role in developing solutions responding to the hardware security challenges, hence strengthening the position of Europe in the field.". , Situação: Concluído; Natureza: Desenvolvimento. , Integrantes: Héctor Pettenghi Roldán - Integrante / CHAVES, RICARDO - Coordenador.

• 2013 - 2016

  Trustworthy Manufacturing and Utilization of Secure Devices, Descrição: This COST action aims at creating a European network of competence and experts on all aspects of hardware security including design, manufacturing, testing, reliability, validation and utilization. The network will play a key role in developing solutions responding to the hardware security challenges, hence strengthening the position of Europe in the field.". , Situação: Concluído; Natureza: Desenvolvimento.

• 2013 - 2016

  Trustworthy Manufacturing and Utilization of Secure Devices, Descrição: This COST action aims at creating a European network of competence and experts on all aspects of hardware security including design, manufacturing, testing, reliability, validation and utilization. The network will play a key role in developing solutions responding to the hardware security challenges, hence strengthening the position of Europe in the field.". , Situação: Concluído; Natureza: Desenvolvimento. , Integrantes: Héctor Pettenghi Roldán - Integrante / CHAVES, RICARDO - Coordenador.

• 2013 - 2016

  Trustworthy Manufacturing and Utilization of Secure Devices, Descrição: This COST action aims at creating a European network of competence and experts on all aspects of hardware security including design, manufacturing, testing, reliability, validation and utilization. The network will play a key role in developing solutions responding to the hardware security challenges, hence strengthening the position of Europe in the field.". , Situação: Concluído; Natureza: Desenvolvimento. , Integrantes: Héctor Pettenghi Roldán - Integrante / CHAVES, RICARDO - Coordenador.

• 2013 - 2016

  Trustworthy Manufacturing and Utilization of Secure Devices, Descrição: This COST action aims at creating a European network of competence and experts on all aspects of hardware security including design, manufacturing, testing, reliability, validation and utilization. The network will play a key role in developing solutions responding to the hardware security challenges, hence strengthening the position of Europe in the field.". , Situação: Concluído; Natureza: Desenvolvimento. , Integrantes: Héctor Pettenghi Roldán - Integrante / CHAVES, RICARDO - Coordenador.

• 2013 - 2016

  Trustworthy Manufacturing and Utilization of Secure Devices, Descrição: This COST action aims at creating a European network of competence and experts on all aspects of hardware security including design, manufacturing, testing, reliability, validation and utilization. The network will play a key role in developing solutions responding to the hardware security challenges, hence strengthening the position of Europe in the field.". , Situação: Concluído; Natureza: Desenvolvimento. , Integrantes: Héctor Pettenghi Roldán - Integrante / CHAVES, RICARDO - Coordenador.

Prêmios