Leonardo Rezende Juracy

Received a bachelor degree from the Pontifical Catholic University of Rio Grande do Sul (PUCRS), Brazil, in Computer Engineering in 2015, an M.Sc. degree from the PUCRS, Brazil, in Computer Science in 2018, and an Ph.D. degree from the PUCRS, Brazil, in Computer Science in 2022. His research interests include design for testability, fault-tolerant designs, asynchronous designs, resilient designs, networks-on-chip, multi-processor systems-on-chip, and hardware accelerators for machine learning applications.

Informações coletadas do Lattes em 09/01/2026

Acadêmico

Formação acadêmica

Doutorado em Ciência da Computação

2018 - 2022

Pontifícia Universidade Católica do Rio Grande do Sul
Título: A Framework for Fast Architecture Exploration of Convolutional Neural Network Accelerators
Fernando Gehm Moraes. Coorientador: Matheus Trevisan Moreira. Bolsista do(a): Coordenação de Aperfeiçoamento de Pessoal de Nível Superior, CAPES, Brasil. Palavras-chave: Convolutional Neural Networks; Convolution Hardware Accelerator; System Simulator; PPA; Design Space Exploration.Grande área: Ciências Exatas e da TerraGrande Área: Ciências Exatas e da Terra / Área: Ciência da Computação / Subárea: Microeletronic. Setores de atividade: Fabricação de equipamentos de informática, produtos eletrônicos e ópticos; Atividades dos serviços de tecnologia da informação.

Mestrado em Ciência da Computação

2016 - 2018

Pontifícia Universidade Católica do Rio Grande do Sul
Título: Testing The Blade Resilient Asynchronous Template: A Structural Approach
, Ano de Obtenção: 2018.Alexandre De Morais Amory.Coorientador: Matheus Trevisan Moreira. Bolsista do(a): Conselho Nacional de Desenvolvimento Científico e Tecnológico, CNPq, Brasil.

Graduação em Engenharia de Computação

2011 - 2015

Pontifícia Universidade Católica do Rio Grande do Sul
Título: Projeto de Uma Célula Latch Testável
Orientador: Alexandre De Morais Amory

Idiomas

Inglês

Compreende Bem, Fala Bem, Lê Bem, Escreve Bem.

Espanhol

Compreende Pouco, Fala Pouco, Lê Pouco, Escreve Pouco.

Português

Compreende Bem, Fala Bem, Lê Bem, Escreve Bem.

Áreas de atuação

Grande área: Outros / Área: Microeletrônica / Subárea: Teste e Tolerância a Falhas.

Grande área: Engenharias / Área: Engenharia Elétrica / Subárea: Circuitos Elétricos, Magnéticos e Eletrônicos/Especialidade: Circuitos Eletrônicos.

Produções bibliográficas

JURACY, LEONARDO R. ; AMORY, ALEXANDRE M. ; MORAES, FERNANDO G. . A Comprehensive Evaluation of Convolutional Hardware Accelerators. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS , v. 70, p. 1149-1153, 2023.
MORAES, FERNANDO GEHM ; JURACY, LEONARDO REZENDE ; GARIBOTTI, RAFAEL . From CNN to DNN Hardware Accelerators: A Survey on Design, Exploration, Simulation, and Frameworks. Foundations And Trends In Electronic Design Automation , v. 13, p. 270-344, 2023.
JURACY, LEONARDO REZENDE ; DE MORAIS AMORY, ALEXANDRE ; MORAES, FERNANDO GEHM . A Fast, Accurate, and Comprehensive PPA Estimation of Convolutional Hardware Accelerators. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS (ONLINE) , v. 69, p. 5171-5184, 2022.
JURACY, LEONARDO REZENDE ; MOREIRA, MATHEUS TREVISAN ; DE MORAIS AMORY, ALEXANDRE ; HAMPEL, ALEXANDRE F. ; MORAES, FERNANDO GEHM . A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS (ONLINE) , v. 68, p. 4783-4795, 2021.
KUENTZER, FELIPE A. ; JURACY, LEONARDO R. ; MOREIRA, MATHEUS T. ; AMORY, ALEXANDRE M. . Testing the blade resilient asynchronous template. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING , v. 106, p. 219-234, 2020.
JURACY, LEONARDO REZENDE ; MOREIRA, MATHEUS TREVISAN ; KUENTZER, FELIPE AUGUSTO ; AMORY, ALEXANDRE DE MORAIS . A DfT Insertion Methodology to Scannable Q-Flop Elements. IEEE Transactions on Very Large Scale Integration (VLSI) Systems , v. 26, p. 1609-1612, 2018.
JURACY, LEONARDO REZENDE ; MOREIRA, MATHEUS TREVISAN ; KUENTZER, FELIPE AUGUSTO ; AMORY, ALEXANDRE DE MORAIS . Optimized Design of an LSSD Scan Cell. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , v. 25, p. 1-4, 2016.
REUSCH, RAFAEL SCHILD ; JURACY, LEONARDO REZENDE ; MORAES, FERNANDO GEHM . Deploying Machine Learning in Resource-Constrained Devices for Human Activity Recognition. In: 2023 XIII Brazilian Symposium on Computing Systems Engineering (SBESC), 2023, Porto Alegre. 2023 XIII Brazilian Symposium on Computing Systems Engineering (SBESC), 2023. p. 1.
REUSCH, RAFAEL SCHILD ; JURACY, LEONARDO REZENDE ; MORAES, FERNANDO GEHM . Assessment and Optimization of 1D CNN Model for Human Activity Recognition. In: 2022 XII Brazilian Symposium on Computing Systems Engineering (SBESC), 2022, Fortaleza/CE. 2022 XII Brazilian Symposium on Computing Systems Engineering (SBESC), 2022. p. 1.
JURACY, LEONARDO R. ; MOREIRA, MATHEUS T. ; AMORY, ALEXANDRE M. ; MORAES, FERNANDO GEHM . A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators. In: 2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS), 2021, Arequipa. 2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS), 2021. p. 1.
KUENTZER, FELIPE A. ; JURACY, LEONARDO R. ; MOREIRA, MATHEUS T. ; AMORY, ALEXANDRE M. . Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template. In: 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2020, Salt Lake City. 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2020. p. 86.
JURACY, LEONARDO ; MOREIRA, MATHEUS TREVISAN ; KUENTZER, FELIPE AUGUSTO ; MORAES, F. G. ; AMORY, ALEXANDRE DE MORAIS . An LSSD Compliant Scan Cell for Flip-Flops. In: IEEE International Symposium on Circuits and Systems, 2018, Florença. IEEE International Symposium on Circuits and Systems, 2018.
KUENTZER, FELIPE AUGUSTO ; JURACY, LEONARDO REZENDE ; AMORY, ALEXANDRE . On-the Reuse of Timing Resilient Architecture for Testing Path Delay Faults in Critical Paths. In: Design, Automation and Testing of Electronic System, 2018, Dresden. Design, Automation and Testing of Electronic System, 2018.
KUENTZER, FELIPE A. ; JURACY, LEONARDO R. ; MOREIRA, MATHEUS T. ; AMORY, ALEXANDRE M. . Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template. In: 2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI), 2018, Bento Gonçalves - RS. 2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI), 2018. p. 1.
JURACY, LEONARDO R. ; LAZZAROTTO, FELIPE B. ; PIGATTO, DANIEL ; CALAZANS, NEY L. V. ; MORAES, FERNANDO G. . XGT4: An industrial grade, open source tester for multi-gigabit networks. In: 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017, Batumi. 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017. p. 252.
WACHTER, EDUARDO ; ERICHSEN, AUGUSTO ; JURACY, LEONARDO ; AMORY, ALEXANDRE ; MORAES, FERNANDO . Runtime fault recovery protocol for NoC-based MPSoCs. In: 2014 15th International Symposium on Quality Electronic Design (ISQED), 2014, Santa Clara. Fifteenth International Symposium on Quality Electronic Design, 2014. p. 132.
WACHTER, EDUARDO ; ERICHSEN, AUGUSTO ; JURACY, LEONARDO ; AMORY, ALEXANDRE ; MORAES, FERNANDO G. . A Fast Runtime Fault Recovery Approach for NoC-Based MPSoCS for Performance Constrained Applications. In: the 27th Symposium, 2014, Aracaju. Proceedings of the 27th Symposium on Integrated Circuits and Systems Design - SBCCI '14, 2014. p. 1.

Histórico profissional

Experiência profissional

2022 - 2023

Chipus Microeletrônica

Vínculo: Celetista, Enquadramento Funcional: Physical Designer, Carga horária: 8

2023 - Atual

EnSilica

Vínculo: Celetista, Enquadramento Funcional: DFT Enginner, Carga horária: 8